                         .module master.c
                         .area data
 0000                 _statusA::
 0000                   .blkb 2
                         .area idata
 0000 0000              .word 0
                         .area data
 0002                 _statusB::
 0002                   .blkb 2
                         .area idata
 0002 0000              .word 0
                         .area data
 0004                 _count::
 0004                   .blkb 2
                         .area idata
 0004 0078              .word 120
                         .area data
 0006                 _dummy::
 0006                   .blkb 2
                         .area idata
 0006 0000              .word 0
                         .area data
                         .area text
 0000                 _T0C2_ISR::
                       ; /*************************************************************
                       ; ECE 473 Lab Assignment #2
                       ; 
                       ; Students: Philip Lechowicz
                       ;           Olamide Adabonyan
                       ; Due Date: 10/28/02
                       ; **************************************************************/ 
                       ; 
                       ; /*************************************************************
                       ; *Header Files
                       ; **************************************************************/
                       ; 
                       ; #include <hc11.h>
                       ; #include <stdio.h>
                       ; #include <stdlib.h>
                       ; #include <Vector.h>
                       ; 
                       ; /*************************************************************
                       ; *Global Variables
                       ; **************************************************************/
                       ; 
                       ; unsigned int statusA = 0;
                       ; unsigned int statusB = 0;
                       ; unsigned int count = 120;
                       ; unsigned int dummy = 0;
                       ; 
                       ; /*************************************************************
                       ; Function: TOC2_ISR
                       ; Purpose: This interrupt occurs 10ms after the switch B is pressed
                       ;          to avoid reading signal while switch is bouncing.  The
                       ;          interrupt inables IC1 and IC2 for the next time the 
                       ;          switch is pressed.  Additionally, it reads PA1; if 
                       ;          high, the switch is pressed and a global status variable 
                       ;          is set to take appropriate action in main.
                       ; Inputs: None
                       ; Outputs: None
                       ; **************************************************************/
                       ; 
                       ; #pragma interrupt_handler   TOC2_ISR
                       ; void T0C2_ISR(void)
                       ; {
                       ;     printf("\nWaited for switch debounce");
 0000 CC01C5            ldd #L4
 0003 BD0000            jsr _printf
                       ;     TMSK1 = 0x06; /*Enable IC2, IC1 Interrupt1, Disable others*/
 0006 C606              ldab #6
 0008 F71022            stab 0x1022
                       ;     TFLG1 = 0x06; /*Clear IC1F and IC2F*/
 000B C606              ldab #6
 000D F71023            stab 0x1023
                       ;     if ((PORTA & 0x02)==0x02) /*Check to see if signal is high*/
                         ; vol
 0010 F61000            ldab 0x1000
 0013 C402              andb #2
 0015 C102              cmpb #2
 0017 2606              bne L5
                       ;         statusB = 1;  /*If high, Set "statusB flag" to take action in main*/
 0019 CC0001            ldd #1
 001C FD0002            std _statusB
 001F                 L5:
                       ;     asm("rti");
 001F 3B                    rti
                       
                       ; }
 0020                 L3:
 0020                   .dbline 0 ; func end
 0020 39                rts
 0021                 _TOC1_ISR::
                       ; 
                       ; /*************************************************************
                       ; Function: TOC1_ISR
                       ; Purpose: This interrupt occurs 10ms after the switch A is pressed
                       ;          to avoid reading signal while switch is bouncing.  The
                       ;          interrupt inables IC1 and IC2 for the next time the 
                       ;          switch is pressed.  Additionally, it reads PA2; if 
                       ;          high, the switch is pressed and a global status variable 
                       ;          is set to take appropriate action in main.
                       ; Inputs: None
                       ; Outputs: None
                       ; **************************************************************/
                       ; 
                       ; #pragma interrupt_handler   TOC1_ISR
                       ; void TOC1_ISR(void)
                       ; {
                       ;     printf("\nWaited for switch debounce");
 0021 CC01C5            ldd #L4
 0024 BD0000            jsr _printf
                       ;     TMSK1 = 0x06; /*Enable IC2, IC1 Interrupts, Disable others*/
 0027 C606              ldab #6
 0029 F71022            stab 0x1022
                       ;     TFLG1 = 0x06;  /*Clear IC1F and IC2F flags*/
 002C C606              ldab #6
 002E F71023            stab 0x1023
                       ;     if ((PORTA & 0x04)==0x04) /*Check to see if signal is high*/
                         ; vol
 0031 F61000            ldab 0x1000
 0034 C404              andb #4
 0036 C104              cmpb #4
 0038 2606              bne L8
                       ;         statusA = 1;  /*If high, Set "statusA flag" to take action in main*/
 003A CC0001            ldd #1
 003D FD0000            std _statusA
 0040                 L8:
                       ;     asm(" rti");
 0040 3B                     rti
                       
                       ; }
 0041                 L7:
 0041                   .dbline 0 ; func end
 0041 3B                rti
 0042                 _TIC2_ISR::
                       ; 
                       ; 
                       ; /*************************************************************
                       ; Function: TIC2_ISR
                       ; Purpose: This Interrupt occurs when switch B (PA1)has a rising or 
                       ;          falling edge.  The tasks of this interrupt are to disable 
                       ;          the IC interrupts, and then enable the OC2 interrupt to 
                       ;          occur 10ms later.  This is to avoid reading the switch 
                       ;          while it is bouncing.
                       ; Inputs: None
                       ; Outputs: None
                       ; **************************************************************/
                       ; 
                       ; #pragma interrupt_handler   TIC2_ISR
                       ; void TIC2_ISR(void)
                       ; {  
                       ;     printf("\nSwitch on PA1 was pressed");       
 0042 CC01AA            ldd #L11
 0045 BD0000            jsr _printf
                       ;     TMSK1 = 0x40; /*Enable OC2 Interrupt, Disable others*/
 0048 C640              ldab #64
 004A F71022            stab 0x1022
                       ;     TOC2 = TCNT + 20000;
                         ; vol
 004D FC100E            ldd 0x100e
 0050 C34E20            addd #20000
 0053 FD1018            std 0x1018
                       ;     TFLG1 = 0x40;  /* Clear OC2F */
 0056 C640              ldab #64
 0058 F71023            stab 0x1023
                       ;     asm(" rti");
 005B 3B                     rti
                       
                       ; }
 005C                 L10:
 005C                   .dbline 0 ; func end
 005C 3B                rti
 005D                 _TIC1_ISR::
                       ; 
                       ; 
                       ; /*************************************************************
                       ; Function: TIC1_ISR
                       ; Purpose: This Interrupt occurs when switch A (PA2)has a rising or 
                       ;          falling edge.  The tasks of this interrupt are to disable 
                       ;          the IC interrupts, and then enable the OC2 interrupt to 
                       ;          occur 10ms later.  This is to avoid reading the switch 
                       ;          while it is bouncing.
                       ; Inputs: None
                       ; Outputs: None
                       ; **************************************************************/
                       ; #pragma interrupt_handler   TIC1_ISR
                       ; void TIC1_ISR(void)
                       ; {
                       ;     printf("\nSwitch on PA2 was pressed");
 005D CC018F            ldd #L13
 0060 BD0000            jsr _printf
                       ;     TMSK1 = 0x80; /*Enable OC1 Interrupt, Disable others*/
 0063 C680              ldab #128
 0065 F71022            stab 0x1022
                       ;     TOC1 = TCNT + 20000;
                         ; vol
 0068 FC100E            ldd 0x100e
 006B C34E20            addd #20000
 006E FD1016            std 0x1016
                       ;     TFLG1 = 0x80;  /* Clear OC1F */
 0071 C680              ldab #128
 0073 F71023            stab 0x1023
                       ;     asm(" rti");
 0076 3B                     rti
                       
                       ; }
 0077                 L12:
 0077                   .dbline 0 ; func end
 0077 3B                rti
 0078                 _RTI_ISR::
                       ; 
                       ; 
                       ; /*************************************************************
                       ; Function: RTI_ISR
                       ; Purpose: This Interrupt occurs at period of 4.096 ms.  The
                       ;          purpose of this interrupt is to toggle PA4 every 1 s or
                       ;          every 244 interrupts.  Thus, a global variable is used
                       ;          to keep a count of the number of rti interrupts that 
                       ;          have occured.  The interrupt only toggles the interrupt
                       ;          when the count has been reduced from 244 to 0.
                       ; Inputs: None
                       ; Outputs: None
                       ; **************************************************************/
                       ; #pragma interrupt_handler   RTI_ISR
                       ; void RTI_ISR(void)
                       ; {
                       ;     //printf("\nRTI_ISR entered");
                       ;     TFLG2 = 0x40;
 0078 C640              ldab #64
 007A F71025            stab 0x1025
                       ;     count = count - 1;
 007D FC0004            ldd _count
 0080 830001            subd #1
 0083 FD0004            std _count
                       ;     if (count == 0)
 0086 FC0004            ldd _count
 0089 260E              bne L15
                       ;     {
                       ;         PORTA = (PORTA ^ 0x10);   /*Toggle PA4*/
                         ; vol
 008B F61000            ldab 0x1000
 008E C810              eorb #16
 0090 F71000            stab 0x1000
                       ;         count = 120;
 0093 CC0078            ldd #120
 0096 FD0004            std _count
                       ;     }
 0099                 L15:
                       ; 
                       ;     //asm(" pulx");
                       ;     //asm(" rti");
                       ; }
 0099                 L14:
 0099                   .dbline 0 ; func end
 0099 3B                rti
 009A                 _main::
                       ; 
                       ; /*************************************************************
                       ; Function: Main
                       ; Purpose: Main first intialiazes all the IC,and RTI interrupts.
                       ;          It then intializes the SPI communication channel. It then
                       ;          goes into a infinite loop writing to the SPDR if the
                       ;          appropriate status variables are set.
                       ;          
                       ; Inputs: None
                       ; Outputs: None
                       ; **************************************************************/
                       ; 
                       ; void main(void)
                       ; {
                       ;     asm("SEI");
 009A 0F                    SEI
                       
                       ;     TMSK1 = 0x06; /*enable IC1 and IC2 interrupts*/
 009B C606              ldab #6
 009D F71022            stab 0x1022
                       ;     TFLG1 = 0x06; /*Clear IC1F and IC2F*/
 00A0 C606              ldab #6
 00A2 F71023            stab 0x1023
                       ;     TCTL2 = 0x3C; /*Set IC1 and IC2 interrupts on any edge*/
 00A5 C63C              ldab #60
 00A7 F71021            stab 0x1021
                       ; 
                       ;     TMSK2 = (TMSK2 | 0x40); /*Enable RTI Interrupt*/
 00AA 18CE1024          ldy #0x1024
 00AE 181C0040          bset 0,y,#64
                       ;     TFLG2 = (TFLG2 | 0x40); /*Clear the RTIF */
 00B2 18CE1025          ldy #0x1025
 00B6 181C0040          bset 0,y,#64
                       ;     PACTL = (PACTL & 0x03); /*Set RTI Interrupt rate for T=4.096 ms*/
 00BA 18CE1026          ldy #0x1026
 00BE 181D00FC          bclr 0,y,#0xfc
                       ; 
                       ;     SPCR = 0x50;               /*Intialize the SPI*/
 00C2 C650              ldab #80
 00C4 F71028            stab 0x1028
                       ;     PORTD = (PORTD | 0x20); /*Enable Device as the master*/
 00C7 18CE1008          ldy #0x1008
 00CB 181C0020          bset 0,y,#32
                       ;     DDRD = (DDRD | 0x38);   /*Initialize PortD*/
 00CF 18CE1009          ldy #0x1009
 00D3 181C0038          bset 0,y,#56
                       ; 
                       ;     RTIvector = &RTI_ISR;
 00D7 CC0078            ldd #_RTI_ISR
 00DA DDEC              std 0xec
                       ;     TOC2vector = &T0C2_ISR;
 00DC CC0000            ldd #_T0C2_ISR
 00DF DDDD              std 0xdd
                       ;     TOC1vector = &TOC1_ISR;
 00E1 CC0021            ldd #_TOC1_ISR
 00E4 FDFFE8            std 0xffe8
                       ;     TIC2vector = &TIC2_ISR; 
 00E7 CC0042            ldd #_TIC2_ISR
 00EA DDE6              std 0xe6
                       ;     TIC1vector = &TIC1_ISR; 
 00EC CC005D            ldd #_TIC1_ISR
 00EF DDE9              std 0xe9
                       ; 
                       ;     asm("CLI");
 00F1 0E                    CLI
                       
                       ; 
                       ;     printf("\nThe start of main");
 00F2 CC017C            ldd #L18
 00F5 BD0000            jsr _printf
 00F8 206A              bra L20
 00FA                 L19:
                       ; 
                       ;     while(1)
                       ;     {
                       ;         printf("\nstart of while loop");
 00FA CC0167            ldd #L22
 00FD BD0000            jsr _printf
                       ;         
                       ;         if (statusA == 1)
 0100 FC0000            ldd _statusA
 0103 1A830001          cpd #1
 0107 2628              bne L23
                       ;         {
                       ;             SPDR = 0x00;
 0109 7F102A            clr 0x102a
 010C 2006              bra L26
 010E                 L25:
 010E CC0001            ldd #1
 0111 FD0006            std _dummy
 0114                 L26:
                       ;             while ((SPSR & 0x80)==0)
 0114 18CE1029          ldy #0x1029
 0118 181F0080F1        brclr 0,y,#128,L25
                       ;             {
                       ;                 dummy = 1;
                       ;             }
                       ;             dummy = SPSR;
                         ; vol
 011D F61029            ldab 0x1029
 0120 4F                clra
 0121 FD0006            std _dummy
                       ;             dummy = SPDR;
                         ; vol
 0124 F6102A            ldab 0x102a
 0127 4F                clra
 0128 FD0006            std _dummy
                       ;             statusA = 0;
 012B CC0000            ldd #0
 012E FD0000            std _statusA
                       ;         }
 0131                 L23:
                       ;         
                       ;         if (statusB == 1)
 0131 FC0002            ldd _statusB
 0134 1A830001          cpd #1
 0138 262A              bne L28
                       ;         {
                       ;             SPDR = 0x01;
 013A C601              ldab #1
 013C F7102A            stab 0x102a
 013F 2006              bra L31
 0141                 L30:
 0141 CC0001            ldd #1
 0144 FD0006            std _dummy
 0147                 L31:
                       ;             while ((SPSR & 0x80)==0)
 0147 18CE1029          ldy #0x1029
 014B 181F0080F1        brclr 0,y,#128,L30
                       ;             {
                       ;                 dummy = 1;
                       ;             }
                       ;             dummy = SPSR;
                         ; vol
 0150 F61029            ldab 0x1029
 0153 4F                clra
 0154 FD0006            std _dummy
                       ;             dummy = SPDR;
                         ; vol
 0157 F6102A            ldab 0x102a
 015A 4F                clra
 015B FD0006            std _dummy
                       ;             statusB = 0;
 015E CC0000            ldd #0
 0161 FD0002            std _statusB
                       ;         }
 0164                 L28:
 0164                 L20:
 0164 2094              bra L19
 0166                 X0:
                       ;     }
                       ; }
 0166                 L17:
 0166                   .dbline 0 ; func end
 0166 39                rts
 0167                 L22:
 0167 0A7374617274206F66207768696C6520   .byte 10,'s,'t,'a,'r,'t,32,'o,'f,32,'w,'h,'i,'l,'e,32
 0177 6C6F6F7000        .byte 'l,'o,'o,'p,0
 017C                 L18:
 017C 0A546865207374617274206F66206D61   .byte 10,'T,'h,'e,32,'s,'t,'a,'r,'t,32,'o,'f,32,'m,'a
 018C 696E00            .byte 'i,'n,0
 018F                 L13:
 018F 0A537769746368206F6E205041322077   .byte 10,'S,'w,'i,'t,'c,'h,32,'o,'n,32,'P,'A,50,32,'w
 019F 6173207072657373656400     .byte 'a,'s,32,'p,'r,'e,'s,'s,'e,'d,0
 01AA                 L11:
 01AA 0A537769746368206F6E205041312077   .byte 10,'S,'w,'i,'t,'c,'h,32,'o,'n,32,'P,'A,49,32,'w
 01BA 6173207072657373656400     .byte 'a,'s,32,'p,'r,'e,'s,'s,'e,'d,0
 01C5                 L4:
 01C5 0A57616974656420666F722073776974   .byte 10,'W,'a,'i,'t,'e,'d,32,'f,'o,'r,32,'s,'w,'i,'t
 01D5 6368206465626F756E636500   .byte 'c,'h,32,'d,'e,'b,'o,'u,'n,'c,'e,0
